Introduction
An AI accelerator passes through about seven sets of hands before it computes anything. At each of them, the number of firms capable of doing the job is one, two or three.
That is not a conspiracy and it is not an accident of market share. It is what happens when every step of a process requires decades of accumulated engineering that does not transfer to a newcomer, and when the capital required arrives years before the first working part does. This post walks down that chain, one link at a time, asking the same three questions at every stop: who makes this, why is there effectively only one, and what would it take for a second to exist?
The answer to the third question is almost never "money". That is the whole point of the walk.
The companion piece to this one, From Token to Transistor, follows a prompt down into the machine — tokens, matrix multiplications, the memory that everything waits on. This one follows the machine back up the chain that built it.
The Design Tools and the Instruction Set
Who makes this. Before a chip is a chip, it is a database. It is written, simulated, placed, routed, verified and signed off inside a software suite — electronic design automation, or EDA — and there are three of them in serious use: Synopsys, Cadence and Siemens EDA. Into that database goes licensed intellectual property, most consequentially CPU cores from Arm. The Arm Neoverse line sits inside AWS Graviton, Google Axion, Microsoft's Azure Cobalt and NVIDIA's Grace CPU Superchip — four of the most-deployed data center processors in the world, none of them made by Arm.
Why so few. Not because the mathematics is secret. Because the design is certified against the tools. A foundry qualifies specific tool versions, running specific extraction and timing decks, for a specific process node; the sign-off that says a chip will work is a sign-off in that toolchain and no other. Swapping suites is not swapping a text editor. It is redoing verification against a different set of models and then asking a foundry to trust the result.
The cleanest demonstration arrived in 2025. In late May, the US Commerce Department required licences for EDA sales to China; Synopsys told staff the rules "broadly prohibit" selling its products there and suspended sales, shipments and new orders. The restrictions were lifted about five weeks later, in early July. What the episode showed is the shape of the link: one memo reached all three suppliers at once, and there was no fourth to call.
What a second would take. For the instruction set, a second already exists — RISC-V is an open architecture and anyone may implement it. What does not exist is the rest: the verified core libraries, the compilers, the operating system support, the decades of silicon that proved the cores work. The instruction set was never the hard part. For EDA, a challenger would have to be qualified by a foundry before a single customer could tape out against it, which means the incumbents' position is defended by the next link in the chain rather than by themselves.
The Foundry
Who makes this. Three companies attempt leading-edge logic: TSMC, Samsung Foundry and Intel. TSMC began volume production of its 2nm-class N2 process in Q4 2025. Intel's first 18A product, Panther Lake, is manufactured at Fab 52 in Arizona. Samsung has a 2nm-class node of its own. Three is the whole list, and the AI accelerators that matter today are overwhelmingly built at one of them.
Why so few. Semiconductor manufacturing owns the mechanism, and it comes down to a learning curve nobody controls. A leading-edge fab's economics are set by defect density — the number of yield-killing specks per square centimetre — and that number falls over quarters, as engineers hunt down sources of contamination that were not in any manual. Copying a recipe does not copy the tacit knowledge that made the recipe work. Building the fab is the cheap, fast part.
And the design cannot simply be moved. It is built against one foundry's process design kit, and porting it means redoing physical design, re-cutting the mask set and re-qualifying the result: quarters to years. This is why chip supply does not reroute the way a shortage of plastic housings does. There is no second supplier to call, because the thing in your hand only fits one line.
What a second would take. Look at how long it takes the incumbent to copy itself. TSMC committed to Arizona in 2020; its first fab there reached high-volume production on N4 in Q4 2024; its second finished construction in 2025 and targets volume production in the second half of 2027; the third targets production "by the end of the decade" (TSMC). Four to seven years from decision to wafers — with the recipe already in hand, the engineers already trained and the money already committed. A genuine newcomer is not on that timeline. It is not on any timeline.
Even within a running fab, time is not compressible: a wafer takes roughly 100 days to cross a 5nm line. Whatever is not already in the fab today is at least a quarter away, no matter what anyone pays.
Beneath the foundry the chain keeps going — polished silicon wafers, photoresists, deposition and etch and metrology tools — and each of those has its own short list of suppliers with its own qualification cycle. The pattern repeats all the way down.
The Scanner
Who makes this. One company. ASML builds every EUV lithography scanner in existence, and every leading-edge logic die and every DRAM die inside an HBM stack is patterned on one.
Why only one. Because ASML is not really the supplier — it is the integrator of a supply chain that has no redundancy either. Zeiss is the only optics house that can polish and coat the multilayer mirrors, to the point that ASML bought a 24.9% stake in Carl Zeiss SMT for €1 billion in 2016 and committed to fund its R&D and capital spending directly (ASML). Trumpf builds the 40-kilowatt CO2 drive laser that vaporises tin droplets fifty thousand times a second to make the light. Remove any one of the three and there is no machine.
What a second would take. Not a patent licence — patents expire, and this barrier has not. Nikon abandoned EUV development in 2011. The programme ASML did not abandon ran from the 1980s to high-volume manufacturing in 2019: roughly thirty years of failures that taught a specific set of people what does not work. A newcomer would be starting that clock from zero, and would also need to find a second Zeiss.
Now the number that ends the argument. ASML recognised revenue on 48 EUV systems in the whole of 2025 — 44 low-NA and 4 High-NA, against 44 systems in 2024 (ASML 2025 Annual Report). Four dozen machines a year, for the entire planet, each taking months to install. That is the physical ceiling on how fast leading-edge capacity can grow, and it is set by how fast Zeiss can polish mirrors — not by how much anyone is willing to pay for a place in the queue.
The Memory
Who makes this. Three firms. In June 2026, NVIDIA's CEO confirmed that SK hynix, Samsung and Micron had all passed certification to supply HBM4 for the Vera Rubin platform (Bloomberg, via Reuters). High bandwidth memory is the component that sets how fast an accelerator can generate tokens, and that is the complete list of who can supply it.
Why so few. The gate is not manufacturing. It is qualification. HBM is not a commodity part you can drop into a socket; a stack must pass the accelerator vendor's thermal, electrical and reliability testing before a single unit ships, and that testing has taken years rather than months. Samsung's 12-layer HBM3E was approved by NVIDIA in September 2025 — "about 18 months after Samsung completed development of the chip", following a string of failures on thermal performance (KED Global).
Read that sentence again with the capital question in mind. Samsung is one of the largest memory manufacturers on Earth. It had finished the chip. It still spent eighteen months in someone else's lab. There is no amount of money that passes a thermal test.
What a second would take. A fourth entrant would need leading-edge DRAM, mastery of through-silicon-via stacking, and then years in a qualification cycle it does not control. And there is a perverse feedback: an HBM gigabyte consumes roughly three times the wafer capacity of a DDR5 gigabyte, because stacking loses yield and the vias eat die area (Tom's Hardware). Every wafer converted to HBM removes about three times as much ordinary DRAM from the world — which is why an AI build-out shows up in the price of laptop memory, and why the memory industry's capacity cannot simply be pointed at HBM without consequences elsewhere.
The Package
Who makes this. Advanced packaging — the step that bonds compute dies and memory stacks onto a shared slab of silicon and seals them into one component — is dominated by TSMC's CoWoS family, with capacity increasingly outsourced to assembly-and-test specialists.
Why it binds. Because it is a separate factory with a separate queue, and for much of the AI build-out it, rather than the wafer fab, has been the thing you could not get. In January 2025 NVIDIA's CEO said the industry's advanced packaging capacity was "probably four times" what had been available less than two years earlier — and it was still the constraint (Taipei Times).
The detail that catches forecasters out: packaging capacity is not fungible between types. Hopper is packaged with CoWoS-S and Blackwell largely with CoWoS-L, and converting a line from one to the other means retooling and requalifying it (Taipei Times, above). Headline capacity can rise while the capacity that matters for a specific product does not. A model with one number in it is modelling the wrong step.
As of mid-2026, TrendForce reports TSMC's CoWoS supply–demand gap at around 20%, projected to narrow to roughly 10% by year end (TrendForce). Treat that pair of figures as perishable — they are revised quarterly. The durable claim underneath them is structural: packaging does not scale just because the fab did.
What a second would take. This is the one link where a second source is actively being stood up: outsourced assembly partners are absorbing overflow. It is still a matter of years, because a packaging line must be qualified for a specific product before it can build it — the same gate as memory, in a different building.
The Software
Who makes this. NVIDIA, and it is not a factory. CUDA has been shipping since 2007, and NVIDIA's own count for its current platform is a community of over 6 million developers and nearly 6,000 CUDA applications (NVIDIA).
Why it is a chokepoint of a different kind. Every link above is made of atoms. It is constrained by capital that must be spent years early, by process knowledge that lives in people's hands, and in one case by the reflectivity of molybdenum. CUDA is constrained by none of that. Nothing in physics forbids a competing software stack. The moat is that every reference implementation in machine learning, every fused kernel, every tutorial and every default in every framework was written against CUDA first — so a challenger does not have to be good, it has to be good enough that a researcher never has to think about it.
What a second would take. This is the only link on the walk where the honest answer is "sustained effort, and possibly not that long". A hardware chokepoint takes a decade to duplicate and then it is duplicated. A software chokepoint can be attacked continuously and never quite falls — but it also cannot be defended by physics, and it erodes at the edges every year. Note the asymmetry, because it cuts against the intuition: the link that looks most like a business advantage is the only one that is not underwritten by the laws of nature.
The Grid
Who makes this. Nobody sells you half a gigawatt next year.
US data centers consumed 176 TWh in 2023 — 4.4% of all US electricity — and are projected to reach 325 to 580 TWh by 2028, or 6.7% to 12% of national consumption (Lawrence Berkeley National Laboratory). That growth has to be connected to something.
Why it binds. Because the queue is the grid, and it is a real queue with real arithmetic. As of the latest Berkeley Lab survey, 2,061 GW of generation and storage capacity was actively seeking transmission interconnection; the median time from interconnection request to commercial operation now exceeds five years; and of the capacity that entered queues between 2000 and 2020, only 13% had come online by the end of 2025 while 75% had withdrawn (LBNL Queued Up, 2025 edition, via APPA).
Generation equipment is queued too. As of April 2025, GE Vernova reported roughly 50 GW of gas turbines under contract or held in slot reservations, with 2026 and 2027 largely sold out; NextEra's CEO put it bluntly — a new gas-fired plant "we can't get it online until 2032" (APPA).
The consequence arrived on the record in November 2025, when Microsoft's CEO said the company had GPUs it could not switch on: the problem was not a shortage of chips but a shortage of "warm shells" — powered, cooled buildings — to plug them into (Tom's Hardware).
What a second would take. There is no second grid. Every other link on this walk can, in principle, be duplicated by someone willing to spend a decade. This one is a shared public system with a shared public queue, and the AI data center is standing in it alongside everyone else.
The Slow Link Moves
Here is the synthesis, and it is the part most analysis gets wrong.
The chain is only as fast as its slowest link, and the slow link moves. Accelerator output is the minimum across wafer starts, HBM stacks, packaging slots and megawatts — and which of those is the minimum has changed repeatedly:
- Wafers, when leading-edge logic capacity was the visible constraint.
- Packaging, through 2023 and 2024 — capacity quadrupled and was still short.
- Memory, as HBM qualification and DRAM wafer allocation became the gate, with knock-on effects across the entire memory market.
- Power, in 2025 and 2026, when the world's largest cloud operator said it had chips in inventory it could not plug in.
Nothing about that sequence was predictable from any single link. Someone forecasting AI compute supply from EUV scanner shipments in 2024 would have missed the packaging bottleneck entirely; someone forecasting from packaging capacity in 2026 would miss the grid. The argmin moves, and it moves for reasons that live in a different industry each time.
The corollary is uncomfortable and worth stating: relieving one bottleneck does not increase output — it just promotes the next one. Quadrupling packaging capacity revealed the memory constraint. Solving memory reveals the interconnection queue. This is what a genuinely serial chain does, and it is why the supply curve for AI compute is so much flatter than the demand curve.
Conclusion
The reader who arrives at this industry from a price chart usually carries one assumption: that a shortage is a money problem, and that enough capital, applied hard enough, will summon supply. Every link on this walk is a refutation.
Capital cannot compress a qualification cycle — Samsung had finished the chip and still spent eighteen months in the lab. It cannot make Zeiss polish mirrors faster, and there are about four dozen scanners a year regardless. It cannot pull a wafer out of a fab before its hundred days are up. It cannot retool a packaging line without requalifying it. It cannot make an interconnection queue five years shorter. And it cannot write six thousand CUDA applications overnight, even though nothing physical prevents it.
What money buys, at every one of these steps, is a place in a queue. That is a real and valuable thing. It is not the same as more chips.
Read the chain forwards and it explains why AI compute supply has been inelastic for four straight years despite the largest capital mobilisation in the industry's history. Read it backwards and it tells you where to look next — not at whichever link is scarce today, but at whichever link becomes scarce the moment today's is fixed.
Sources
- ASML 2025 Annual Report — financials
- ASML — ZEISS and ASML Strengthen Partnership for Next Generation of EUV Lithography (2016)
- TRUMPF — EUV drive laser
- TechCrunch — US imposes new rules to curb semiconductor design software sales to China
- CNBC — US lifts chip software curbs on China
- Arm — A comprehensive guide to understanding Arm Neoverse
- Focus Taiwan — TSMC officially begins 2nm chip volume production in Q4 2025
- Intel — Panther Lake, the first AI PC platform built on 18A
- TSMC Arizona
- ECIA / Electronics Sourcing — Understanding lead times
- Bloomberg via Reuters — Nvidia certifies Samsung, SK hynix and Micron for Vera Rubin HBM4 supply
- KED Global — Samsung's 12-layer HBM3E passes NVIDIA qualification
- Tom's Hardware — HBM is eating your RAM
- Taipei Times — Nvidia CEO on advanced packaging capacity
- TrendForce — TSMC CoWoS supply-demand gap seen narrowing from 20% to 10% by end-2026
- NVIDIA — Rubin CPX announcement (CUDA ecosystem figures)
- Lawrence Berkeley National Laboratory — 2024 United States Data Center Energy Usage Report
- Lawrence Berkeley National Laboratory — Queued Up, 2025 edition
- American Public Power Association — Backlog of power plants seeking grid connection
- American Public Power Association — Gas turbine backlogs come to the forefront
- Tom's Hardware — Microsoft CEO on GPUs sitting in inventory for lack of power