Term tag: NVIDIA

Advanced Packaging

CoWoS, chiplets and 3D stacking — how compute dies and memory become one accelerator, and the assembly step that has actually gated AI chip supply.

AI Data Center

Why AI facilities are measured in megawatts rather than servers — power density, liquid cooling, and the grid connection that has become the real constraint.

CUDA

NVIDIA's software layer for GPUs — the programming model that turned graphics cards into AI hardware, and the real reason rivals with comparable silicon lose.

Distributed Training

How one model is trained across thousands of GPUs — data, tensor and pipeline parallelism, and why the network rather than the chip becomes the bottleneck.

High Bandwidth Memory (HBM)

Stacked DRAM bonded beside the GPU die — the scarce component that gates AI accelerator supply, and why bandwidth rather than capacity is the constraint.

Interconnect (NVLink, InfiniBand)

The wiring that moves data between AI chips: on-package memory, NVLink inside a server, InfiniBand between them — and why each tier is far slower than the last.

Matrix Multiplication (GEMM)

The one operation that consumes most of an AI model's compute — and the reason AI chips are built the way they are, from tensor cores to systolic arrays.

NVIDIA GPU for AI

Why AI training runs on NVIDIA rather than cheaper silicon — tensor cores, NVLink, and the software that decides how much of the datasheet you actually get.

Semiconductor Manufacturing

How an AI chip is actually made — wafers, process nodes, yield and the foundry model — and why supply cannot simply respond to a spike in demand.