Term tag: AI Hardware

Advanced Packaging

CoWoS, chiplets and 3D stacking — how compute dies and memory become one accelerator, and the assembly step that has actually gated AI chip supply.

AI Energy Consumption

How much energy an AI query really uses, how training compares with serving, and how to read the numbers without believing either the hype or the panic.

Application-Specific Integrated Circuit (ASIC)

A chip wired for one job. Why Google builds TPUs and bitcoin abandoned GPUs — the volume-and-time bet behind custom silicon, with the break-even maths.

EUV Lithography

The machines that print advanced chips with 13.5 nm light — how they work, why only one company makes them, and what that chokepoint means.

GPU Computing

Why a graphics chip runs AI: a GPU spends its transistors on arithmetic instead of on making one thread fast — and what that trade wins and costs.

High Bandwidth Memory (HBM)

Stacked DRAM bonded beside the GPU die — the scarce component that gates AI accelerator supply, and why bandwidth rather than capacity is the constraint.

Interconnect (NVLink, InfiniBand)

The wiring that moves data between AI chips: on-package memory, NVLink inside a server, InfiniBand between them — and why each tier is far slower than the last.

Matrix Multiplication (GEMM)

The one operation that consumes most of an AI model's compute — and the reason AI chips are built the way they are, from tensor cores to systolic arrays.

Memory Wall

Why LLM inference waits on memory rather than maths — arithmetic intensity, the roofline, and the one fact that explains HBM scarcity and the price of a token.

Neural Processing Unit (NPU)

An NPU is a fixed-function matrix engine inside a phone or laptop chip that runs AI models at a few watts — and why TOPS is the wrong number to…

NVIDIA GPU for AI

Why AI training runs on NVIDIA rather than cheaper silicon — tensor cores, NVLink, and the software that decides how much of the datasheet you actually get.

Quantum Computing (QC)

Quantum computing uses qubits — held in superposition and entangled — for exponential speedups on a narrow set of problems, not general computing.

Semiconductor Manufacturing

How an AI chip is actually made — wafers, process nodes, yield and the foundry model — and why supply cannot simply respond to a spike in demand.

Speculative Decoding

A small model drafts tokens and a large one verifies them in parallel — how LLM inference gets several times faster with mathematically identical output.

Tensor Processing Unit (TPU)

A TPU is Google's custom ASIC for the matrix multiplications in neural networks: a systolic array that reuses each value instead of refetching it.