---
source: 'https://howaiworks.ai/glossary/semiconductor-manufacturing'
section: glossary
title: Semiconductor Manufacturing
description: >-
  How an AI chip is actually made — wafers, process nodes, yield and the foundry
  model — and why supply cannot simply respond to a spike in demand.
tags:
  - Semiconductor
  - AI Chips
  - AI Hardware
  - Chip Technology
  - Manufacturing
  - AI Infrastructure
  - NVIDIA
category: Infrastructure & Hardware
datePublished: '2026-07-13'
lastUpdated: '2026-07-13'
---

# Semiconductor Manufacturing

> How an AI chip is actually made — wafers, process nodes, yield and the foundry model — and why supply cannot simply respond to a spike in demand.

## Definition

**A chip is not assembled. It is printed — hundreds of copies at once, onto a polished 300-millimetre
disc of silicon, through several hundred process steps that take about three months.** Nothing is
put together from parts. Layers of material are grown, patterned with light, and etched away, up to
a hundred times over, until the transistors are simply *there* in the silicon. The single number
that decides what the finished chip costs is what fraction of those copies come out working.

And **nothing on a "3nm" chip is three nanometres.** The term "has no direct relation to any actual
physical feature (such as gate length, metal pitch, or gate pitch) of the transistors"
([Wikipedia](https://en.wikipedia.org/wiki/3_nm_process)). It is the marketing name of a process
generation. The tightest metal pitch at that node is around **24 nm** — eight times the name. Node
names have not described a physical dimension for a quarter of a century, and treating them as if
they do is the most common mistake made about this industry.

## How It Works

### From wafer to packaged die

The starting material is a mirror-polished silicon disc, 300 mm across — an area of
`π × 150² ≈ 70,686 mm²`, enough to hold hundreds of chips side by side.

Onto it the fab runs a loop: deposit a film, coat it with light-sensitive resist, project a pattern
through a mask, develop, etch away what the pattern exposed, clean, measure, repeat. ASML — which
builds the machines that do the projecting — says the process "involves hundreds of steps" and that
"modern chips can have up to 100 layers, which all need to align on top of each other with nanometer
precision"
([ASML](https://www.asml.com/en/technology/all-about-microchips/how-microchips-are-made)). The
patterning step is where the exotic physics lives, and [EUV lithography](https://howaiworks.ai/glossary/euv-lithography)
owns that story; here it is one step in the loop, run many times.

The loop is slow. Fab cycle time — wafer in, finished wafer out — runs "from roughly 40 days at 28nm
to 100 days at 5nm"
([ECIA](https://electronics-sourcing.com/2025/04/14/understanding-lead-times/)), and the
[SIA](https://www.semiconductors.org/chipmakers-are-ramping-up-production-to-address-semiconductor-shortage-heres-why-that-takes-time/)
puts total time to a finished chip, including assembly and test, at up to 26 weeks. Then the wafer is
probed to find which dies work, sawn into individual dies, and packaged — bonded to a substrate,
often alongside memory. That last stage has become a bottleneck in its own right, and [advanced
packaging](https://howaiworks.ai/glossary/advanced-packaging) owns it.

### What a node name actually is

If "3nm" is not a length, what is it? A label for a generation of transistor and interconnect design
that is, roughly, denser and more efficient than the one before it. The measurable quantities are the
pitches — at the 3 nm node, a contacted gate pitch of about **48 nm** and a tightest metal pitch of
about **24 nm** (IRDS 2021, via [Wikipedia](https://en.wikipedia.org/wiki/3_nm_process)) — and, more
usefully, transistor density and defect rate. No standards body polices the names, so they are not
comparable between foundries either: one company's "2nm" and another's are claims about competitive
positioning, not measurements.

### Yield is the whole economics

Defects — a speck of contamination, a mis-etched line — land on the wafer essentially at random. A
die containing even one of them is scrap. So the probability that a die survives falls with its
area, and it falls faster than linearly.

The standard tool is **Murphy's yield model**, published in 1964 and still the default when you have
no better data: `Y = ((1 − e^(−A·D₀)) / (A·D₀))²`, where `A` is die area in cm² and `D₀` is defect
density in defects per cm² ([iSine](https://isine.com/resources/die-yield-calculator/)). Take a real
defect density: at TSMC's 2020 Technology Symposium, its N5 process was reported at **0.10 to 0.11
defects per square centimetre** as high-volume manufacturing ramped
([DVHardware](https://www.dvhardware.net/article73608.html)). Use `D₀ = 0.10`.

Now put two dies on that same wafer.

- **A small die: 100 mm² (1.00 cm²)** — the scale of a phone processor.
- **A large die: 814 mm² (8.14 cm²)** — the size NVIDIA quotes for the GH100 die inside the H100, "80
  billion transistors, a die size of 814 mm²" on TSMC's 4N process
  ([NVIDIA](https://developer.nvidia.com/blog/nvidia-hopper-architecture-in-depth/)).

**Step 1 — how many fit.** The standard gross-die approximation
([AnySilicon](https://anysilicon.com/die-per-wafer-formula-free-calculators/)) is
`π·d²/4S − π·d/√(2S)`; the second term is the dies lost at the round edge.

- 100 mm²: `70,686/100 − 942/14.1 = 707 − 67 ≈ **640** dies`
- 814 mm²: `70,686/814 − 942/40.3 = 86.8 − 23.4 ≈ **63** dies`

**Step 2 — how many survive.**

- 100 mm²: `A·D₀ = 0.10`, so `Y = ((1 − e^(−0.10))/0.10)² = **90.6%**`
- 814 mm²: `A·D₀ = 0.814`, so `Y = ((1 − e^(−0.814))/0.814)² = **46.8%**`

**Step 3 — good dies per wafer.**

- 100 mm²: `640 × 0.906 ≈ **580**`
- 814 mm²: `63 × 0.468 ≈ **30**`

**Step 4 — the conclusion.** The wafer costs the same whichever die you print on it. So cost per
*working* chip goes as 1 ÷ (good dies per wafer): `580 ÷ 30 ≈ **19×**`. The big die uses **8.1 times**
the silicon and costs roughly **20 times** as much per working part. That gap — the difference
between 8× and 20× — is the yield tax, and it is the reason an AI accelerator is priced like a small
car rather than like eight phone chips.

### The tax is not fixed; it compounds

Push the defect density to `D₀ = 0.20` — a plausible figure for a node still climbing its learning
curve, since TSMC's N5 sat above 0.10 before volume ramp:

- Small die: yield falls 90.6% → 82.1%, good dies 580 → 526. **A 9% loss.**
- Large die: yield falls 46.8% → 24.4%, good dies 30 → 15. **Output halves.**

The same process regression that a phone chip barely notices destroys half of an accelerator line.
This is why large dies are never launched on the newest node: they wait a year or two for `D₀` to
come down. The learning curve is not a schedule anyone controls, and it cannot be bought.

### Which is why the industry cut the die up

Split that 814 mm² design into four 204 mm² tiles. Each tile now yields `((1 − e^(−0.204))/0.204)² =
81.8%`, and a wafer holds about 300 of them, giving `300 × 0.818 ≈ 245` good tiles — enough for
**about 61 four-tile products**, against 30 monolithic ones. Roughly twice the accelerators from the
same wafer, from nothing but geometry. (The estimate is generous: the tiles need extra area for
die-to-die interfaces, and the package has a yield of its own.)

There is also a hard ceiling. Lithography exposes one rectangular field at a time, and the industry's
standard field is **26 × 33 mm — 858 mm²**
([ASML](https://www.asml.com/en/products/duv-lithography-systems/twinscan-nxt1980di)). The H100's 814
mm² is already 95% of it. Past that line a single die is not expensive, it is *impossible*, and
splitting the design stops being an optimisation and becomes the only option. What to do with the
pieces afterwards is [advanced packaging](https://howaiworks.ai/glossary/advanced-packaging)'s problem.

## Real-World Applications

**Pricing an AI accelerator.** The arithmetic above is not a metaphor for accelerator cost; it *is*
accelerator cost. A large die on a leading-edge node, plus [HBM
stacks](https://howaiworks.ai/glossary/high-bandwidth-memory) bonded beside it, plus a packaging step with its own yield:
every layer of that stack is another yield multiplier, and they compound.

**Selling the failures.** Because a defect usually kills one region rather than the whole die,
manufacturers disable the broken part and sell the rest. NVIDIA's full GH100 design has **144
streaming multiprocessors**; the H100 SXM5 product ships with **132** enabled, and the PCIe version
with 114 ([NVIDIA](https://developer.nvidia.com/blog/nvidia-hopper-architecture-in-depth/)). That
product line-up is a yield map. When you buy the cheaper variant of a chip, you are usually buying a
die that failed its way into a lower bin — which is a bargain for you and a rescued wafer for the
manufacturer.

**Deciding where a design gets made.** Only a handful of firms in the world can produce leading-edge
logic at all, and a chip design is not portable between them: it is built against one foundry's
process design kit, and moving it means redoing physical design, re-cutting a mask set and
re-qualifying the result — quarters to years of work. This is why a chip shortage does not reroute
the way a shortage of, say, plastic housings does. There is no second supplier to call, and the
design in your hand only fits one line. Export controls and subsidy programmes are policy acting on
exactly this chokepoint, and they only make sense once you know it exists.

## Key Concepts

- **A yield figure without a die area is meaningless.** TSMC announced roughly **80% average yield**
  for N5 in December 2019 — on **17.92 mm² test chips**
  ([Wikipedia](https://en.wikipedia.org/wiki/5_nm_process)). That is a real number and it tells you
  almost nothing about an 814 mm² die on the same process, because the two differ by a factor of 45
  in exposed area. Always ask "on what die?"
- **D₀ is a learning curve, not a constant.** Defect density falls over quarters as engineers hunt
  down sources of contamination and variation. It is the most closely guarded number a foundry has,
  and it is why a process gets cheaper with age even though nothing about the design changed.
- **The wafer is the unit of cost; the die is the unit of value.** Almost every economic oddity here
  follows from that mismatch — binning, chiplets, the premium on small dies, and the fact that a bad
  month for defect density is a bad quarter for shipments.
- **The reticle limit is physics, not policy.** 26 × 33 mm is the field a scanner can expose. No
  amount of capital buys a bigger monolithic die.

## Challenges

**What breaks: planning as though chip supply is elastic.** This is the expensive one. A team, or a
government, sees demand rise and assumes output will follow, because that is how nearly every other
market behaves. It does not behave that way here. A wafer already in the fab needs about 100 days to
come out. New capacity needs years: TSMC committed to Arizona in 2020 and began high-volume
production on N4 in **Q4 2024**; its second fab there finished construction in 2025 and targets
volume production in the **second half of 2027**; the third broke ground in April 2025 and targets
production "by the end of the decade"
([TSMC](https://www.tsmc.com/static/abouttsmcaz/index.htm)). On any horizon shorter than that,
capacity is a constant. Demand can therefore only express itself as price and as queue — which is
exactly what an AI hardware shortage looks like from the outside, and why "someone will just build
more fabs" is not a plan you can put in a budget.

**What breaks: comparing node names.** Two foundries' "2nm" processes are not measurements of the
same thing, and neither is a measurement of anything. Compare on transistor density, power and
shipped yield; a chip built on the newer-sounding node can be denser, sparser, later or worse.

**What breaks: assuming cost scales with area.** Doubling a die's area does not double its cost — in
the regime AI accelerators live in it does considerably worse, and a decision that adds 15% to die
area can add far more than 15% to the price of a working part. It is why a monolithic design that
looks elegant on a whiteboard is often uneconomic on a wafer.

**Yield knowledge does not transfer.** A new fab running a proven process still starts partway down
the learning curve: new tools, new water, new technicians. Copying a recipe does not copy the tacit
knowledge that made it work — which is why erecting the building is the cheap, fast part of building
a fab.

## Future Trends

The constraint is migrating out of the fab. As dies split into tiles and accelerators grow more
[HBM](https://howaiworks.ai/glossary/high-bandwidth-memory) stacks, the step limiting how many AI chips exist has been
shifting from wafer starts to [advanced packaging](https://howaiworks.ai/glossary/advanced-packaging) capacity — a
different set of factories, with their own multi-year build times.

Lithography will make the reticle problem worse before it makes it better. High-NA EUV, the next
generation of patterning tool, buys its resolution partly by *halving* the exposure field to 26 ×
16.5 mm. Sharper printing, half the canvas — which pushes even mid-sized designs toward multi-die
construction. [EUV lithography](https://howaiworks.ai/glossary/euv-lithography) covers what that machine is doing and why.

And the names will keep drifting. Gate-all-around transistors and backside power delivery are real
architectural changes arriving in this decade's nodes, and they will be marketed under numbers that
correspond to nothing. Read the density figure. Ignore the nanometres.

## Frequently Asked Questions

### Is anything on a '3nm' chip actually 3 nanometres?

No. Wikipedia's summary of the industry position is blunt: the term '3 nanometer' has no direct relation to any actual physical feature — not gate length, not metal pitch, not gate pitch — of the transistors. It is the marketing name of a process generation. The tightest metal pitch at that node is about 24 nm, an order of magnitude larger than the name.

### Why are AI accelerators so expensive to manufacture?

Because they are enormous dies, and defects are random. At a defect density of 0.1 per square centimetre, a 100 mm2 die yields about 91% and an 814 mm2 accelerator die yields about 47%. The accelerator uses roughly 8 times the silicon but costs about 20 times as much per working chip, because the wafer costs the same either way and far fewer good dies come off it.

### Why can't foundries just make more chips when demand spikes?

A wafer takes roughly 100 days to move through a leading-edge fab, and a new fab costs tens of billions and takes years. TSMC's second Arizona fab finished construction in 2025 and is targeting volume production in the second half of 2027. Within any given year, capacity is essentially fixed, so a demand spike shows up as price and lead time rather than as more chips.

### What is defect density and why does it matter?

It is the average number of yield-killing defects per square centimetre of wafer, usually written D0. It falls over quarters as a process matures — TSMC's 5nm process was around 0.10 to 0.11 defects per square centimetre as high-volume manufacturing ramped. Because a die fails if it contains even one defect, D0 and die area together determine yield, and yield determines cost.

### Why did AI chips move to chiplets?

Yield. One defect scraps one die, so splitting a big design into several smaller dies means each defect destroys less silicon. It also gets around the reticle limit: lithography can only expose a 26 x 33 mm field, about 858 mm2, and a single die cannot exceed it. The stitching back together is the job of advanced packaging.

### Can a chip design be moved to a different foundry?

Not quickly. A design is built against one foundry's process design kit, and moving it means re-doing physical design, re-making the mask set and re-qualifying the result — work measured in quarters to years, not weeks. This is why chip supply does not reroute the way most supply chains do.

## Related

### Related terms

- [EUV Lithography](https://howaiworks.ai/glossary/euv-lithography)
- [Advanced Packaging](https://howaiworks.ai/glossary/advanced-packaging)
- [Application-Specific Integrated Circuit (ASIC)](https://howaiworks.ai/glossary/application-specific-integrated-circuit)
- [GPU Computing](https://howaiworks.ai/glossary/gpu-computing)
- [High Bandwidth Memory (HBM)](https://howaiworks.ai/glossary/high-bandwidth-memory)
- [Tensor Processing Unit (TPU)](https://howaiworks.ai/glossary/tensor-processing-unit)

---

Source: https://howaiworks.ai/glossary/semiconductor-manufacturing — HowAIWorks.ai